发明名称 THREE SOURCE OPERAND FLOATING POINT ADDITION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
摘要 A processor of an aspect includes a decode unit to decode a three source floating point addition instruction indicating a first source operand having a first floating point data element, a second source operand having a second floating point data element, and a third source operand having a third floating point data element. An execution unit is coupled with the decode unit. The execution unit, in response to the instruction, stores a result in a destination operand indicated by the instruction. The result includes a result floating point data element that includes a first floating point rounded sum. The first floating point rounded sum represents an additive combination of a second floating point rounded sum and the third floating point data element. The second floating point rounded sum represents an additive combination of the first floating point data element and the second floating point data element.
申请公布号 WO2015147895(A1) 申请公布日期 2015.10.01
申请号 WO2014US39600 申请日期 2014.05.27
申请人 INTEL CORPORATION 发明人 ESPASA, ROGER;SOLE, GUILLEM;FERNANDEZ, MANEL
分类号 G06F7/38;G06F9/30 主分类号 G06F7/38
代理机构 代理人
主权项
地址