Test Circuits

摘要

Described herein is a feed forward equalizer that is configured to operate in a normal operational mode and in a test operational mode. The feed forward equalizer has an input port and an output port which are used for the normal operational mode. A test input port and a test output port are provided in the feed forward equalizer, and are used for the test operational mode. Buffers may be provided for matching the impedance of respective ones of the input, output, test input, and test output ports. The feed forward equalizer allows testing during development, and once mounted in an integrated circuit, without interfering with the normal operational mode.

主权项

1. A feed forward equalizer circuit comprising:
an input port for receiving an input signal; a first line connected to the input port; an output port for providing an output signal; a second line connected to the output port; a first tap element connected between the first line and the second line at respective line nodes; at least one second tap element connected between the first line and the second line at respective line nodes; at least one first delay element connected to the first line between the first tap element and the at least one second tap element; at least one second delay element connected to the second line between the at least one second tap element and the first tap element; a test input port connected to the first line and a test output port connected to the second line, and wherein the test input port and the test output port are respectively connected to first and second line nodes associated with the at least one second tap element.