发明名称 |
DRAM Cells and Methods of Forming Silicon Dioxide |
摘要 |
Some embodiments include methods of forming silicon dioxide in which silicon dioxide is formed across silicon utilizing a first treatment temperature of no greater than about 1000° C., and in which an interface between the silicon dioxide and the silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. Some embodiments include methods of forming transistors in which a trench is formed to extend into monocrystalline silicon. Silicon dioxide is formed along multiple crystallographic planes along an interior of the trench utilizing a first treatment temperature of no greater than about 1000° C., and an interface between the silicon dioxide and the monocrystalline silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. A transistor gate is formed within the trench, and a pair of source/drain regions is formed within the monocrystalline silicon adjacent the transistor gate. Some embodiments include DRAM cells. |
申请公布号 |
US2015279694(A1) |
申请公布日期 |
2015.10.01 |
申请号 |
US201514740072 |
申请日期 |
2015.06.15 |
申请人 |
Micron Technology, Inc. |
发明人 |
Srivastava Shivani;Shrotri Kunal;Ahmed Fawad |
分类号 |
H01L21/324;H01L29/423;H01L29/66;H01L27/108;H01L29/78 |
主分类号 |
H01L21/324 |
代理机构 |
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代理人 |
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主权项 |
1. A method of forming a transistor, comprising:
forming a trench extending into monocrystalline silicon, the trench exposing multiple crystallographic planes of the monocrystalline silicon; forming silicon dioxide along the multiple crystallographic planes along an interior surface of the trench utilizing a first treatment temperature of less than or equal to about 1000° C.; annealing an interface between the silicon dioxide and the monocrystalline silicon utilizing a second treatment temperature which is at least about 1050° C.; forming a transistor gate within the trench and spaced from the monocrystalline silicon by the silicon dioxide; and forming a pair of source/drain regions within the monocrystalline silicon; with the source/drain regions being on opposing sides of the transistor gate from one another. |
地址 |
Boise ID US |