SEMICONDUCTOR ARRANGEMENT WITH THERMAL INSULATION CONFIGURATION

摘要

Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided herein. A semiconductor arrangement comprises a cap wafer, a microelectromechanical systems (MEMS) wafer, and a complementary metal-oxide-semiconductor (CMOS) wafer. The MEMS wafer comprises a thermal insulator air gap formed between a sensing layer and a membrane. An ambient pressure chamber is formed between the CMOS wafer and the membrane of the MEMS wafer. The ambient pressure chamber is configured as a second thermal insulator air gap. The thermal insulator air gap and the second thermal insulator air gap protect portions of the semiconductor arrangement, such as the MEMS wafer, from heat originating from the CMOS wafer, which can otherwise damage such portions of the semiconductor arrangement. In some embodiments, one or more buffer layers are formed over the cap wafer as stress buffers.

主权项

1. A semiconductor arrangement, comprising:
a complementary metal-oxide-semiconductor (CMOS) wafer; a microelectromechanical systems (MEMS) wafer formed over the CMOS wafer, the MEMS wafer comprising a first thermal insulator air gap between a sensing layer and a membrane; an ambient pressure chamber formed between the CMOS wafer and the membrane of the MEMS wafer; and a cap wafer formed over the MEMS wafer, the cap wafer comprising a pressurized chamber having a pressure different than an ambient air pressure.