发明名称 LOCK ELISION WITH BINARY TRANSLATION BASED PROCESSORS
摘要 Generally, this disclosure provides systems, devices, methods and computer readable media for detection and exploitation of lock elision opportunities with binary translation based processors. The device may include a dynamic binary translation (DBT) module to translate a region of code from a first instruction set architecture (ISA) to translated code in a second ISA and to detect and elide a lock associated with a critical section of the region of code. The device may also include a processor to speculatively execute the translated code in the critical section. The device may further include a transactional support processor to detect a memory access conflict associated with the lock and/or critical section during the speculative execution, roll back the speculative execution in response to the detection, and commit the speculative execution in the absence of the detection.
申请公布号 WO2015148099(A1) 申请公布日期 2015.10.01
申请号 WO2015US19562 申请日期 2015.03.10
申请人 INTEL CORPORATION 发明人 KELM, JOHN H.;NEELAKANTAM, NAVEEN;KHARTIKOV, DENIS M.
分类号 G06F9/38;G06F9/30 主分类号 G06F9/38
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