发明名称 CONTROL APPARATUS AND CONTROL METHOD
摘要 A control unit stores data used in a process to a shared cache memory. The control unit provides a shared queue in a memory space of the shared cache memory and performs LRU control with the use of the shared queue. The control unit also provides a local queue in the memory space of the shared cache memory. The control unit enqueues a CBE (management information) for a cache page used by a core in a process to the local queue. The control unit dequeues a plurality of CBEs from the local queue upon satisfaction of a predetermined condition, and enqueues the dequeued CBEs to the shared queue.
申请公布号 US2015278114(A1) 申请公布日期 2015.10.01
申请号 US201514636825 申请日期 2015.03.03
申请人 FUJITSU LIMITED 发明人 Kumabe Takuro;Kobayashi Akihito;Sakai Motohiro;Matsumura Shinichiro;Ohyama Takahiro
分类号 G06F12/12;G06F12/08 主分类号 G06F12/12
代理机构 代理人
主权项 1. A control apparatus, comprising: a processor including two or more cores with local cache memories; and a shared cache memory that is shared between the cores, wherein the processor performs a procedure including: enqueuing management information for unit data used in a process performed by a core and stored in the shared cache memory to a local queue assigned to the core, dequeuing a plurality of pieces of the management information from the local queue, and enqueuing the dequeued pieces of the management information to a shared queue that is shared between the two or more cores.
地址 Kawasaki-shi JP