DOUBLE CONSECUTIVE ERROR CORRECTION

摘要

Double consecutive error correction is described. An integrated circuit with double consecutive error correction logic includes a data storage structure operative to store a set of data and a first error correction code that corresponds to the set of data. The set of data includes multiple data bits. The first error correction code was generated using a generator matrix having multiple bit groups, each bit group including a unique set of bit positions. The integrated circuit also includes an error correction code generator operative to generate, using the generator matrix, a second error correction code that corresponds to the set of data. The integrated circuit further includes a comparator operative to generate a comparison result of the first error correction code and the second error correction code. The integrated circuit includes a data corrector operative to correct two consecutive data bits of the set of data.

主权项

1. An integrated circuit comprising:
a data storage structure operative to store a set of data and a first error correction code that corresponds to the set of data, wherein the set of data comprises a plurality of data bits, wherein the first error correction code was generated using a generator matrix having a plurality of bit groups, each bit group comprising a unique combination of bit values; an error correction code generator operative to generate a second error correction code based on the generator matrix; a comparator operative to generate a comparison result of the first error correction code and the second error correction code; and a data corrector operative to correct two consecutive data bits of the set of data when the comparison result corresponds to a result of an exclusive-or (XOR) operation performed on two consecutive bit groups of the generator matrix.