Low-power dual-edge-triggered storage cell with scan test support and clock gating circuit therefor

摘要

A storage cell (1) having a pulse generator (5) and a storage element (6) is proposed. The storage element input (7) is connected to receive a data input signal (DIN). The storage element output (9) is connected to provide a data output signal (DOUT). The storage element (6) is operable in one of a data retention state and a data transfer state in response to a storage control signal (SC) received from the pulse generator (5). The pulse generator (5) is connected to receive a clock signal (CK) with rising and falling clock signal edges (13, 14) and is adapted to provide control pulses (15, 16) in the storage control signal (SC). Each control pulse (15, 16) has a leading edge (17) and a trailing edge (18). The control pulses (15, 16) have a polarity suited to invoke the data transfer state on their leading edges (17). The novel feature is that the pulse generator (5) is adapted to initiate a rising-edge control pulse (15) when receiving a rising clock signal edge (13) and to initiate a falling-edge control pulse (16) when receiving a falling clock signal edge (14). In this way, a dual-edge-triggered flip-flop may be made using only combinatorial logic circuitry and one level- or single-edge-triggered storage element (6). The storage cell (1) has low power consumption, facilitates scan testing and can be used by existing design tools and test equipment.