SEMICONDUCTOR WAFER HAVING EMBEDDED ELECTROPLATING CURRENT PATHS TO PROVIDE UNIFORM PLATING OVER WAFER SURFACE

摘要

A semiconductor wafer having multi-layer metallization structures that are fabricated to include embedded interconnection structures which serve as low-resistance electroplating current paths to conduct bulk electroplating current fed to portions of a metallic seed layer at peripheral surface regions of the wafer to portions of the metallic seed layer at inner/central surface regions of the semiconductor wafer to achieve uniformity in metal plating in chip regions across the wafer.