发明名称 TIMER CIRCUIT AND SIGNAL PROCESSING CIRCUIT EQUIPPED WITH THE SAME
摘要 PROBLEM TO BE SOLVED: To provide a timer circuit for repeatedly generating an interrupting signal in an uncertain cycle by reducing the load of a CPU. SOLUTION: This timer circuit for setting a reload value according to a time to be measured, and for performing a count operation on the basis of the set reload value is provided with: a memory for storing a plurality of reload values; a reload value address generation circuit for generating a reload value address showing the storage destination of each of the plurality of reload values on the memory; a counter for referring to the reload value address generated by the reload value address generation circuit for performing a count operation on the basis of the reload value read from the memory; and a timer control circuit for controlling the update of the reload value address in the reload value address generation circuit and the reading of the reload value from the memory to the counter. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008090613(A) 申请公布日期 2008.04.17
申请号 JP20060270984 申请日期 2006.10.02
申请人 SANYO ELECTRIC CO LTD;SANYO SEMICONDUCTOR CO LTD 发明人 TOMIZAWA SHINICHIRO
分类号 G06F11/30 主分类号 G06F11/30
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