| 摘要 |
This invention relates to a method and processor ( 19 ) for power analysis in digital circuits. The method incorporates a main processor ( 19 ) and an associative memory mechanism ( 101 a, 101 b, 102, 104, 105, 106 ), the associative memory mechanism comprising a plurality of associative arrays ( 101 a, 101 b), an input value register ( 102 ), at least one result register ( 104 ) and a memory block area ( 29 ). A circuit design is transformed into a functionally equivalent model format suitable for processing in the associative array and thereafter input vectors are applied to the circuit and a record is kept of the inputs and or the outputs on each of the gates in the circuit over a specified time period. In this way, it is possible to calculate the leakage power dissipation as well as both the toggle dynamic power and the transition dynamic power.
|
