发明名称 DEVICE, METHOD AND PROGRAM FOR CREATING LOGIC CIRCUIT VERIFICATION DATA
摘要 PROBLEM TO BE SOLVED: To provide a device for creating logic circuit verification data, capable of easily forming verification data of a logic circuit. SOLUTION: The device 1 for creating logic circuit verification data comprises a verification data retrieval part 41 for retrieving and extracting, based on input and output timing designation data 23 designating an input and output timing of the logic circuit, data of verification points from input verification point data 25; and a verification data alignment part 42 for aligning and outputting the data of verification points extracted by the retrieval part 41 while adding information of timing. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008090622(A) 申请公布日期 2008.04.17
申请号 JP20060271166 申请日期 2006.10.02
申请人 TOSHIBA CORP 发明人 SHIGETA YOSHINORI;MICHINAKA HIDEJI;OGAMI AKIHIRO;SUZUMURA TATSUHIRO;TAKEGAWA SATOSHI;NAKAYAMA HIROMITSU;WATANABE KIWAMU;OGAWA TAKAYA;UEHASHI MASASHI
分类号 G06F17/50 主分类号 G06F17/50
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