DATA PROCESSING HARDWARE

摘要

This invention generally relates to data processing hardware, and more particularly to hardware accelerators and related methods for matrix factorisation especially non- negat ive matrix factorisation (NMF). Embodiments of the invention are particularly useful for driving electroluminescent displays such as OLED displays. A matrix factorisation hardware accelerator for determining a pair of factor matrices (R;C) which when multiplied together approximate a target matrix, the hardware accelerator comprising: an input to receive an input data matrix representing said target matrix; a first factor matrix memory for storing row and column data for a first factor matrix (R), said first factor matrix memory having a plurality of first data buses each associated with a respective block of said first factor matrix memory for accessing first factor matrix column data stored in the block; a second factor matrix memory for storing row and column data for a second factor matrix (C), said second factor matrix memory having a plurality of second data buses each associated with a respective block of said second factor matrix memory for accessing second factor matrix row data stored in the block; a matrix of processor blocks, each processor block having: a first processor block data bus coupled to one of said first data buses, a second processor block data bus coupled to one of said second data buses, and a result data output; a processor memory block for storing a portion of a matrix (Q) representing a difference between a product of said pair of factor matrices and said target matrix; and a data processor comprising at least one multiply-add unit, said data processor having a first input coupled to said processor memory block and a second input coupled to one or both of said first and second processor block data buses and having an output coupled to said result data output; and control circuitry to control writing of data from said input into said processor memory blocks of said matrix of processor blocks, to control reading of data from said first and second factor matrix memories for provision to said matrix of processor blocks, and to control writing of data derived from said result data outputs back to said first and second factor matrix memories to perform said matrix factorisation.