发明名称 Increasing memory supply voltage in response to an error
摘要 A memory circuit 100 comprises memory cells 412 with error detection circuitry 220 to detect errors in the memory cells. When an error is detected, control circuitry 230 increases the supply voltage to one or more of the memory cells. The circuit may use charge pump circuits 440 to increase the voltage. The voltage may be increased for a subset of the cells which includes the cell in which the error was detected. The voltage may be increased for cells which have been accessed. The error detection circuit may correct the error. The memory cells may be static random access memory cells. The memory may be the cache memory of a processor.
申请公布号 GB2442846(A) 申请公布日期 2008.04.16
申请号 GB20070019014 申请日期 2007.09.28
申请人 INTEL CORPORATION 发明人 MUHAMMAD KHELLAH;DINESH SOMASEKHAR;YIBIN YE
分类号 G06F11/10;G06F1/26;G11C29/00 主分类号 G06F11/10
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