STACKED MEMORY AND METHOD FOR FORMING THE SAME

摘要

A stacked memory device and a method for forming the same are provided to reduce the dimension of a contact hole by reducing the depth of the contact hole in a peripheral region. At least two semiconductor layers(100,200) respectively include memory cell arrays. A first transistor(230L) is arranged on a peripheral region of the top semiconductor layer. A second transistor(230H) is arranged on a peripheral region of the semiconductor layer between the top semiconductor layer and the bottom semiconductor layer or is arranged on a peripheral region of the bottom semiconductor layer. The first transistor is a low voltage transistor. The second transistor is a high voltage transistor. The memory cell arrays of the respective semiconductor layers include memory cell strings(MCS), string selective transistors(SST), and ground selective transistors(GST). The memory cell strings are serially connected to memory cells. The string selective transistors and the ground selective transistors are connected to memory cells at both ends of the memory cells.