发明名称
摘要 An electronic camera in which an analog signal output from a CCD image sensor is AD-converted and digital processing is performed on the AD-converted by an A/D converter in an analog front end, and the AD-converted signal DMA-transferred to a RAM through line memories in a signal processor. The signal processor controls a basic operating clock signal generated from a clock signal generation circuit so that the frequency of the clock signal is reduced during a read period in which processing including AD conversion of the analog signal output from the CCD image sensor is performed.
申请公布号 JP4061645(B2) 申请公布日期 2008.03.19
申请号 JP20030053244 申请日期 2003.02.28
申请人 发明人
分类号 G03B7/091;H04N5/232;G03B7/28;H04N5/225;H04N101/00 主分类号 G03B7/091
代理机构 代理人
主权项
地址