发明名称 STRUCTURE AND METHOD TO USE LOW k STRESS LINER TO REDUCE PARASITIC CAPACITANCE
摘要 A low k stress liner, which replaces conventional stress liners in CMOS devices, is provided. In one embodiment, a compressive, low k stress liner is provided which can improve the hole mobility in pFET devices. UV exposure of this compressive, low k material results in changing the polarity of the low k stress liner from compressive to tensile. The use of such a tensile, low k stress liner improves electron mobility in nFET devices.
申请公布号 US2008048271(A1) 申请公布日期 2008.02.28
申请号 US20060467186 申请日期 2006.08.25
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 YANG HAINING;LI WAI-KIN
分类号 H01L29/76;H01L21/8234;H01L21/8238 主分类号 H01L29/76
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