发明名称 |
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING CLOCK LATENCY ACCORDING TO REORDERING OF BURST DATA |
摘要 |
In an embodiment, a semiconductor memory device includes a clock latency that can be controlled responsive to whether or not an output order of burst data is reordered. The semiconductor memory device may comprise a control unit and a latency control unit. The control unit may generate a latency control signal having a logic level that varies depending on whether or not an output order of burst data is reordered. The latency control unit may control a latency value in response to the latency control signal. The semiconductor memory device and the method of controlling the latency value responsive to a reordering of the burst data allow for an optimally fast memory access time.
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申请公布号 |
US2008052482(A1) |
申请公布日期 |
2008.02.28 |
申请号 |
US20070775780 |
申请日期 |
2007.07.10 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
CHOI JOO-SUN;JUNG WON-CHANG;LEE HI-CHOON;YIM SUNG-MIN;PARK CHUL-WOO;BAE WON-IL |
分类号 |
G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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