发明名称 FILTER PROCESSING APPARATUS, MULTIPLIER, AND MOTION COMPENSATION PROCESSING DEVICE
摘要 <P>PROBLEM TO BE SOLVED: To reduce the amount of hardware without deteriorating processing speed. <P>SOLUTION: As for filters #1 and #2, a filter computing unit 1 carries out product sum operation of input data f0-f2 and respective two or more filter factors consisting of the filters #1 and #2 by using booth algorithm. The filter computing unit 1 comprises: two or more partial product generation units 3 and 4 for generating one or more partial product by inputting one or more group data consisting of filter factors corresponding to input data and the above input data; an adder 10 for generating the summation of partial products; and selectors 7 and 8 which input group data into either one or both of the partial product generation units 3 and 4. For example, in the case where a part of the partial product to be generated from one-group data cannot be generated by the partial product generation unit 3, the selectors 7 and 8 input the group data into the partial product generator of the other partial product generation unit 4 along with the partial product generation unit 3 so as to generate the partial product. <P>COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2007324980(A) 申请公布日期 2007.12.13
申请号 JP20060153363 申请日期 2006.06.01
申请人 NEC ELECTRONICS CORP 发明人 KATAYAMA YOICHI
分类号 H04N19/50;G06F7/533;H04N19/42;H04N19/423;H04N19/44;H04N19/503;H04N19/513;H04N19/593;H04N19/60;H04N19/61;H04N19/625;H04N19/80;H04N19/82;H04N19/91 主分类号 H04N19/50
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