| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To decrease a parasitic capacitance load of a boost circuit in low voltage applications. <P>SOLUTION: A word line driver for flash memory uses an NMOS circuit for decreasing a parasitic capacity load. A delay scheme which delays turn-on of a source-drain circuit of a driver for a short time after turn-on of a gate of a driver transistor, allows the gate capacitance of the driver transistor to provide an extra boost. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
