发明名称 INTEGRATED CIRCUIT DESIGN DEVICE AND PROGRAM
摘要 PROBLEM TO BE SOLVED: To display a circuit element in a layout by suppressing any dead space to be generated in the layout of an integrated circuit. SOLUTION: An input device designates border lines 221 to 223 between grids associated with circuit elements whose alignment release is designated by a matrix display device 201 of a display device to designate the alignment release of circuit elements associated with each grid in a direction along the border lines 221 to 223 (corresponding to border lines 213 to 215 of a layout display device 202). The circuit elements are rearranged so that any space is formed due to alignment release, and the circuit elements after alignment release are displayed in the arrangement display region 202. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2007323151(A) 申请公布日期 2007.12.13
申请号 JP20060149792 申请日期 2006.05.30
申请人 JEDAT INNOVATION:KK 发明人 ONO NOBUTADA;MINESHIMA MITSUTOSHI
分类号 G06F17/50 主分类号 G06F17/50
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