发明名称 ALTERNATIVE INTEGRATION SCHEME FOR CMOS S/D SiGe PROCESS
摘要 A method for fabricating a semiconductor device with adjacent PMOS and NMOS devices on a substrate includes forming a PMOS gate electrode with a PMOS hardmask on a semiconductor substrate with a PMOS gate dielectric layer in between, forming an NMOS gate electrode with an NMOS hardmask on a semiconductor substrate with an NMOS gate dielectric layer in between, forming an oxide liner over a portion of the PMOS gate electrode and over a portion of the NMOS gate electrode, forming a lightly doped N-Halo implant, depositing a nitride layer over the oxide liner, depositing photoresist on the semiconductor substrate in a pattern that covers the NMOS device, etching the nitride layer from the PMOS device, wherein the etching nitride layer leaves a portion of the nitride layer on the oxide liner, etching semiconductor substrate to form a Si recess, and depositing SiGe into the Si recesses, wherein the SiGe and the nitride layer enclose the oxide liner. The method can also include implanting in the semiconductor substrate a source and drain region for the PMOS.
申请公布号 US2007287244(A1) 申请公布日期 2007.12.13
申请号 US20070739099 申请日期 2007.04.24
申请人 APPLIED MATERIALS, INC., A DELAWARE CORPORATION 发明人 SHEN MEIHUA;CHO YONAH;KAWAGUCHI MARK N.;NOURI FARAN;MA DIANA X.
分类号 H01L21/8236 主分类号 H01L21/8236
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