发明名称 CLOCK SELECTING CIRCUIT AND SYNTHESIZER
摘要 <p>An optimum clock signal is selected from among a plurality of clock signals in a short time. A reference-clock counter (1a) counts clock pulses in an inputted reference clock signal (REF). A clock counter (1b) counts clock pulses in one of the plurality of clock signals which is selected by a selection unit (1e) and frequency-divided by a frequency divider (2). An instruction-signal output unit (1c) outputs a plurality of comparison-instruction signals during an interval in which a difference occurs between the counts of two of the plurality of clock signals having the closest frequencies. A comparison unit (1d) compares the count of the reference-clock counter (1a) and the count of the clock counter (1b). The selection unit (1e) selects a clock signal by a binary search according to the result of the comparison.</p>
申请公布号 EP1865603(A1) 申请公布日期 2007.12.12
申请号 EP20050727371 申请日期 2005.03.31
申请人 FUJITSU LTD. 发明人 MARUTANI, MASAZUMI
分类号 H03L7/18;H03L7/10;H03L7/14 主分类号 H03L7/18
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