| 摘要 |
<p>A semiconductor memory device comprising: bit lines (BL, /BL) in pairs; a sense amplifier (400-0) that is connected to each pair of the bit lines (BL, /BL); a first memory cell (MC00) that is connected to one bit line (BL) of each pair of the bit lines (BL, /BL); a second memory cell (MC10) that is connected to the other bit line (/BL) of each pair of the bit lines (BL, /BL), and stores inverted data of data stored in the first memory cell (MC00); a word line (WL) connected to every other pair of the bit lines (BL, /BL); an open-close column gate (40, 41) that connects the bit lines (BL, /BL) to a data bus (DB); and a control circuit (15, CL) that controls the column gate (40, 41) to open before the sense amplifier (400-0) is activated in a data write operation. The semiconductor memory device of the present invention is also characterized by including a control circuit (11) that controls the sense amplifier (400-0, 400-1) to start a pull-down operation after starting a pull-up operation. Such a device has an operation control method and a circuit structure that allows a higher process rate, less power consumption, and a smaller chip area.
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