| 摘要 |
PROBLEM TO BE SOLVED: To provide a processor device aiming at improvement in operation process efficiency of a processor. SOLUTION: A bus selection part 14 is connected to individual control buses B1-Bn which are provided for each processor 11-1 to 11-n and a common control bus Bc connected to a data memory 13, and by selecting an individual control bus based on selection directions, it allows access to the data memory 13 of the selected processor. A bus arbitration part 15 recognizes a bus request of the processor 11-1 to 11-n to the individual control buses B1-Bn and notifies the selection directions to the bus selection part 14. A bus monitoring part 16 counts the number of bus requests and the number of bus request conflicts, respectively and sums up them. The part determines priority when the processors 11-1 to 11-n access the data memory 13 from the summing result, transmits a weight direction signal to the processor with low priority, and delays access start time to the data memory 13. COPYRIGHT: (C)2007,JPO&INPIT
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