| 摘要 |
A data processing apparatus includes a plurality of CPU modules each including a CPU. Each of the plurality of CPU module includes a clock source, a clock counter, an I/O module, a first data adder, and a timing adjuster. The first data adder reads a value of the clock counter, adds a predetermined offset value to the read value to generate a timing value, and adds the generated timing value to the packet designated to the CPU. The timing adjuster adjusts timing of transmitting the packet to the CPU, based on the timing value of the packet received from the first data adder and the value of the clock counter.
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