发明名称 COINCIDENCE-ACCUMULATION TYPE ADDER
摘要 FIELD: digital computer engineering. ^ SUBSTANCE: adder realizes operations of addition, left and right code shift, inversion, modulus two addition, logical addition, multiplication. Each bit of adder contains two RS-triggers, nine AND elements, five OR elements, five NOT elements, eight control buses and information input. Adder features construction of each bit only on basis of two RS-triggers and new circuits for realization of additional operations. Total number of inputs of logical elements of one bit equals 36, in average one realized operation requires about 5 inputs (Quine price). ^ EFFECT: expanded functional capabilities with minimal hardware costs. ^ 1 dwg, 1 tbl
申请公布号 RU2306596(C1) 申请公布日期 2007.09.20
申请号 RU20060105435 申请日期 2006.02.21
申请人 VLASOV BORIS MIKHAJLOVICH;LOGINOV VLADIMIR ALEKSANDROVICH;KOMAROV ALEKSEJ FEDOROVICH;KRASNOV ALEKSANDR VASIL'EVICH 发明人 VLASOV BORIS MIKHAJLOVICH;LOGINOV VLADIMIR ALEKSANDROVICH;KOMAROV ALEKSEJ FEDOROVICH;KRASNOV ALEKSANDR VASIL'EVICH
分类号 G06F7/50 主分类号 G06F7/50
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