| 摘要 |
<p>A decoder circuit wherein a high-speed, definite output can be achieved without increasing the entire size of a decoder body part, which comprises a plurality of decoder essential circuits, and also without increasing the size of a circuit, which drives the decoder body part, itself. The definite output operation and the cancellation output operation are separated from each other. During the cancellation output operation, a reset-dedicated PMOS transistor (13) is used to drive an inverter (9) in the last stage for performing a cancellation output. The waveform blunting of the cancellation output can be improved. During the definite output operation, an inverter (8), which drives the inverter (9) in the last stage, increases the size of an NMOS transistor, which contributes to the definite output, while, contrarily, reducing the size of a PMOS transistor that contributes to the cancellation output. The waveform blunting of the definite output is improved without changing the capability of an inverter (7) in the preceding stage, that is, without increasing the load for the decoder input, whereby the high-speed, definite output can be achieved.</p> |
