发明名称 Multiplier and arithmetic unit
摘要 A multiplier has a multiplication array in which partial products are generated by performing multiplication between a multiplier and a multiplicand, and a partial product control circuit which generates an enable signal for activating an effective region in the multiplication array corresponding to effective figures of the multiplier and the multiplicand. The effective figures depend on the format of the multiplier and the multiplicand. The partial product control circuit controls the status of the enable signal according to a multiplication command designating the format. The multiplication array is constituted by a dynamic circuit. The dynamic circuit in an initial stage of the multiplication array has a switch which is turned on/off by the enable signal. When the enable signal is ineffective, the switch is turned off and a discharging operation in the dynamic circuit is stopped.
申请公布号 US2007203964(A1) 申请公布日期 2007.08.30
申请号 US20070709784 申请日期 2007.02.23
申请人 NEC CORPORATION 发明人 OSADA TAKASHI
分类号 G06F7/52 主分类号 G06F7/52
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