Method for accelerating the RC extraction in integrated circuit designs

摘要

The present invention provides a system and method for accelerating the resistance and capacitance (RC) extraction process by performing parallel and distributed processing. The method includes the dividing of a given integrated circuit (IC) design into a limited number of non-overlapping tile blocks, distributing tile blocks to standard RC extraction tools, and processing all tiles in parallel by these tools. A tile block includes all information for performing accurate RC extraction. Thereafter, resulting parasitic RC information is assembled to form a complete parasitic RC model for the entire IC.