| 摘要 |
A digital video system ( 2 ) is disclosed, in which an analog input video signal is sampled at an optimum sample phase (P<SUB>nc</SUB>), and converted to a digital datastream for display. A phase-locked loop ( 12 ) generates a plurality of sample clock phases. One of the sample clock phases (P<SUB>nc</SUB>) is applied to an analog-to-digital converter ( 10 ), which digitizes the analog input video signal accordingly. Phase alignment circuitry ( 20 ) is provided that includes three sample-and-hold circuits ( 22 b, 22 c, 22 a) that sample the analog input video signal, in parallel with the analog-to-digital converter ( 10 ), at times before, at, and after the current sample clock phase used by the analog-to-digital converter ( 10 ). The earlier and later sampled voltages are compared against the current sampled voltages to generate difference voltages that are each compared against a threshold voltage (V<SUB>thr</SUB>). The numbers of times that the difference voltages exceed the threshold voltage over a field or frame is analyzed according to various techniques, to determine whether and in which direction to adjust the position of the current sample clock phase within the pixel period.
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