| 摘要 |
<p>A trigger architecture (105) includes a plurality of parallel analog-to-digital converters (ADCs) (106,107,108,109,110) operative to garner data samples (116,117,118,119,120) in parallel from an input signal (113) at different times in a clock signal period. The trigger architecture also includes a logic block (111) comprising a plurality of digital comparators (301,302,303,304,305), which are adapted to compare each of the data samples to one or more threshold values in parallel. A measurement system (100) including the trigger architecture (105) is described.</p> |
