发明名称 METHOD AND STRUCTURE FOR DOUBLE LINING FOR SHALLOW TRENCH ISOLATION
摘要 A method of forming an integrated circuit device structure having a design rule of less than 0.13 micron. The method includes providing a substrate and forming a pad oxide layer overlying the substrate. The method includes forming a nitride layer overlying the pad oxide layer and patterning the nitride layer and pad oxide layer. A trench structure is formed within a thickness of the substrate using the patterned nitride layer and pad oxide layer as hard mask. The method forms a first thickness of liner oxide within the trench structure using at least thermal oxidation of an exposed region of the trench structure to cover the trench structure. Such thermal oxidation causes a rounding region near corners of the trench structure. The method selectively removes the thickness of liner oxide within the trench structure. The method forms a second thickness of liner oxide within the trench structure using at least thermal oxidation to cover the trench structure. The thermal oxidation causes a further rounding of the rounded region near corners of the trench structure. The method also selectively removes the patterned nitride layer while the second thickness of liner oxide protects the substrate in the trench region.
申请公布号 US2007087519(A1) 申请公布日期 2007.04.19
申请号 US20060536458 申请日期 2006.09.28
申请人 SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION 发明人 CHI-KANG LIU;WANG XIN;LI ZE K.
分类号 H01L21/76;H01L29/76;H01L29/94;H01L31/00 主分类号 H01L21/76
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