| 摘要 |
A power wiring structure realizes low inductance and is applicable to a semiconductor device. <??>The power wiring structure employs two switching elements that are connected in series and are complementarily turned on and off. Ends of the switching elements are connected to power lines extending from a power source. A node between the switching elements is connected to an output line U that is connected to load. The power lines are a high-potential power line P and a low-potential power line N. The lines P, N, and U are each a wide electrode with the width thereof greater than the thickness thereof. The electrodes are layered one upon another in a thickness direction in order of P, U, and N to form a three-layer wide electrode structure. <??>A current of the same value as and oppositely oriented from a current flowing through the output line U flows through the output line P or N, to cancel magnetic fields generated by the currents, thereby effectively reducing wiring inductance. <IMAGE> |
