发明名称 Method and system for safe and efficient chip power down drawing minimal current when a device is not enabled
摘要 Certain embodiments of a method and system for safe and efficient power down and drawing minimal current when a device is not enabled may comprise receiving within a network adapter chip (NAC) a signal that indicates a reduced power mode. Based on this signal, the NAC may control an off-chip voltage source that provides reduced voltage to circuitry within the NAC. The off-chip voltage source, which may comprise a first PNP transistor and a second PNP transistor, may reduce a voltage to a first voltage and a second voltage. The NAC may also reduce current through the off-chip voltage source to approximately zero amperes and an output voltage of the off-chip voltage source to approximately zero volts. The first voltage and/or the second voltage may be fed back to control the output voltage and current of the off-chip voltage source.
申请公布号 US2006288245(A1) 申请公布日期 2006.12.21
申请号 US20050269419 申请日期 2005.11.08
申请人 LEE JONATHAN F 发明人 LEE JONATHAN F.
分类号 G06F1/32 主分类号 G06F1/32
代理机构 代理人
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