发明名称 Package structure of chip and the package method thereof
摘要 For a package structure of chip and the formation thereof, adhesive, conductive and metal layers are positioned on a substrate. The portions of the conductive and metal layers are removed to form multitudes of trenches therethrough, so that the metal layer is divided into chip supporters and conductive nodes isolated or electrical coupled each another. A chip is positioned on each of the chip supporter and electrically coupled to the conductive nodes. A molding compound covers the conductive layer, metal layer and chip. Then the substrate is removed. A dicing process as is applied with each chip or chipset as a unit to form the package structures of chip. There are advantages over improvement of reliability, reduction of package height, improve of level characteristic and heat dissipation, which may be applied to different types of semiconductor package.
申请公布号 US2006284292(A1) 申请公布日期 2006.12.21
申请号 US20050154696 申请日期 2005.06.17
申请人 CHENG JOSEPH 发明人 CHENG JOSEPH
分类号 H01L23/02 主分类号 H01L23/02
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