Flash memories and processing systems including the same

摘要

A memory may include first and second buffer memories and a memory core. The memory core may include memory blocks each having a plurality of pages and a page buffer for reading data from a selected memory block. A control logic may control the first and second buffer memories and the memory core. The control logic may have a register for storing address and command information of the memory core. The control logic may control the memory core so that data read periods for pages of the selected memory block are carried out according to the stored address and command information. The control logic may control the first and second buffer memories and the memory core so that data in the page buffer may be transferred to the first and/or second buffer memories during the data read periods. The control logic may deactivate an interrupt signal when data in the page buffer is transferred to the first and/or second buffer memory and may activate the interrupt signal when data in the first and/or second buffer memory is transferred to an external storage.