发明名称 DMA CIRCUIT AND COMPUTER SYSTEM
摘要 PROBLEM TO BE SOLVED: To scale down a circuit and reduce development man-hours in a DMA circuit that operates a plurality of DMA channels in parallel. SOLUTION: A channel manager circuit (5) reads out control information of each DMA channel in a control memory (40) sequentially, analyzes it, and carries out state processing (DMA control) according to the sequence of the divided DMA control. The channel manager circuit (5) updates the control information, writes it back to the control memory (40), and controls a plurality of the DMA channels in a time-sharing system. This DMA circuit realizes scaling down of the circuit, which contributes to the cost reduction, and reduction of development man-hours. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006268753(A) 申请公布日期 2006.10.05
申请号 JP20050089641 申请日期 2005.03.25
申请人 FUJITSU LTD 发明人 HANEDA MITSUMASA;OGAWA YUICHI;YOSHIDA TOSHIYUKI;HANAOKA YUJI
分类号 G06F13/28 主分类号 G06F13/28
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