| 摘要 |
A clock recovery system includes a rough clock generator, which yields a rough clock signal, based upon logic level transitions exhibited by a data signal. The rough clock signal is supplied to a phase locked loop having an adjustable order of frequency response, an adjustable corner frequency, an adjustable natural frequency, and/or an adjustable damping factor. The clock recovery system includes control parameters that, when properly adjusted, suppress non-ideal effects of components within the clock recovery system, and also permit the frequency response of the phase locked loop to be returned to a desired response.
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