| 摘要 |
A method ( 150 ) for defining an aligned logic cell grid and interconnect layout of a semiconductor integrated circuit having a logic cell ( 12 ) is disclosed. The interconnect layout is resized in accordance with a highest common denominator of an initial routing pitch ( 24 ) of the interconnect layout and a transistor pitch ( 14 ) of the logic cell. The cell grid is aligned with the resized routing pitch ( 124 ) which provides efficient routing density and transistor performance, minimises excess transistor area and wire routing waste while maximising cell packing density.
|
