| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a frequency division circuit for suppressing the amount of jitters that arise with an output signal. <P>SOLUTION: This circuit comprises a circuit module 3 that activates series-connected D-FF7, 9 and 11, by using a reference clock signal as an input signal S0 and produces a first frequency division signal S7, by dividing an input signal S0 at any frequency division ratio selected by a frequency division ratio determination signal S21, a circuit module 45 that activates series-connected D-FF47, 49, 51 and 53, by using the first frequency division signal S7 as a reference clock signal and produces an output signal S57, by dividing the first frequency division signal S7, according to a frequency division ratio (division of frequency by 8), based on the number of series-connected D-FFs and an OR circuit 55 that produces the above frequency division ratio determination signal S21, based on the D-FF output of the circuit module 45 and the 4/5 selection signal S24. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
