| 摘要 |
PROBLEM TO BE SOLVED: To provide an architecture for reducing an additional circuit for a test by shortening test time, and achieving test facilitation design to an extremely large-scale circuit by providing the test facilitation design applicable even when a bit width of a data signal conductor is nonuniform. SOLUTION: A place with insufficient data line is marked on a control path and an observation path of respective circuit elements (Step 1006). A virtual test pin is allocated to a place having no mark on the circuit element side (Step 1008). The circuit is added so that the insufficient data line is connected to the external input-output side at test (Step 1010). The test facilitation design is performed by regarding circuit elements as one circuit element by detecting the circuit elements for constituting a reconvergence branching structure. A decoder is divided with every compression test plan table, and a test plan is grouped so as to provide the compression test plan for optimizing the test length and a scale of a test controller. COPYRIGHT: (C)2006,JPO&NCIPI
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