| 摘要 |
PROBLEM TO BE SOLVED: To more improve ESD resistance on a circuit side where a signal is received. SOLUTION: An inverter circuit INV1 is connected to a ground wiring GND1 for power supply, and is connected to a power supply wiring VDD1 via a PMOS transistor MP5. An inverter circuit INV2 is connected to a ground wiring GND2 and a power supply wiring VDD2 for power supply, and an input node is connected to an output node of the inverter circuit INV1. Further, it is connected to the ground wiring GND1 and the ground wiring GND2 via a protective element PE0. In ordinary operation, an output of an inverter circuit INV3 becomes the H level, and the output of an inverter circuit INV4 becomes an L level to switch on the PMOS transistor MP5. In application of the ESD the power supply wiring VDD2 is in floating, and the output of the inverter circuit INV4 becomes the H level to switch off the PMOS transistor MP5, hereby preventing a current following the application of the ESD from flowing into the inverter circuit INV2. COPYRIGHT: (C)2006,JPO&NCIPI |
