发明名称 High-speed verifiable semiconductor memory device
摘要 A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection circuit connected to one terminal of the memory cell charges one terminal of the memory cell to a predetermined potential. The detection circuit detects the voltage of one terminal of the memory cell based on a first detection timing, and further, detects the voltage of one terminal of the memory cell based on a second detection timing.
申请公布号 US2006126392(A1) 申请公布日期 2006.06.15
申请号 US20050297467 申请日期 2005.12.09
申请人 发明人 SHIBATA NOBORU
分类号 G11C16/06;G11C16/04 主分类号 G11C16/06
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