| 摘要 |
The invention concerns a semiconductor integrated memory (100) comprising a first memory zone (40a), a second memory zone (40b), as well as first address connections (A0, A1,..., An) and a second address connection (An+ 1). A second address signal (AS2) applied to the second address connection specifies whether the system should access the first or the second memory zone, while first address signals (AS1a,..., AS1n) specify, at the first address connections, which memory cell, inside the first or the second memory zone, the system should access. In a first memory configuration, all the address connections (A0, A1,..., An, An+1) are externally controlled by means of address signals for specifying whether the system should access a memory cell in the first or in the second memory zone (40a, 40b). In a second memory configuration, only the first address connections (A0, A1,..., An) are externally controlled, while a signalling bit regulates, in a mode register (51), access to the first or the second memory zone, thus enabling access to the second memory zone (40b), even when it is impossible to control the second address connection address (An+1) externally.
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