发明名称 DESIGN METHOD AND DESIGN PROGRAM FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To attain the shortening of process time of automatic layout wiring, improvement in production yield and improvement in cell characteristics while preventing generation of a terminal which is not wire-connected in layout wiring. SOLUTION: In S13, an operation for temporarily substituting a set wiring modification object cell WC (minimum rule cell MC) by a prefer rule cell PC is performed. Since a free space of cells is present in the area of a block B1a, the situation that a predetermined pitch cannot be kept by mutual interference of the prefer rule cells PC after substitution can be prevented. Even if the cells after substitution are mutually interfered, the cells can be moved to non-interfering positions because the free space of cells is present, to prevent the situation that the predetermined pitch cannot be kept. When processing to all wiring modification object cells WC is completed, rewiring is performed in S20. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006155182(A) 申请公布日期 2006.06.15
申请号 JP20040344097 申请日期 2004.11.29
申请人 FUJITSU LTD 发明人 NISHIWAKI AKIFUMI
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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