发明名称 Methods of manufacture of a via structure comprising a plurality of conductive elements and methods of forming multichip modules including such via structures
摘要 A method of forming a multiconductor via includes forming at least one seed layer in at least one through-hole of a substrate, selectively patterning the seed layer to form a plurality of laterally separated regions, and depositing metal upon the regions. Alternatively, a through-hole may be substantially filled with dielectric material, a plurality of smaller, through holes may be formed in the dielectric material, and conductive material may be deposited in the smaller holes. Another method includes forming laterally separated protruding structures in a cavity of a substrate, depositing conductive material over the structures and dielectric material between the structures, and thinning the substrate. Alternatively, conductive nanotubes may be formed in the cavity, and dielectric material may be deposited that surrounds the nanotubes. A method of forming a multichip module includes forming at least one via extending through a plurality of stacked dice that includes a plurality of conductive elements.
申请公布号 US2006125109(A1) 申请公布日期 2006.06.15
申请号 US20060351006 申请日期 2006.02.08
申请人 发明人 KIRBY KYLE K.;FARNWORTH WARREN M.
分类号 H01L23/48 主分类号 H01L23/48
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