STRAINED SILICON, GATE ENGINEERED FERMI-FETS

摘要

A field effect transistor includes a strained silicon channel in a substrate, source/drain regions in the substrate at opposite ends of the strained silicon channel, a gate insulating layer on the strained silicon channel, and a gate on the gate insulating layer. The doping of the strained silicon channel, the doping of the substrate and/or the depth of the strained silicon channel are configured to produce nearly zero vertical electric field in the gate insulating layer and in the strained silicon channel surface at a threshold voltage of the field effect transistor. Moreover, the gate is configured to provide a gate work function that is close to a mid-bandgap of silicon. Accordingly, a Fermi-FET with a strained silicon channel and a gate layer with a mid-bandgap work function are provided. Related fabrication methods using epitaxial growth also are described.