| 摘要 |
<p>A novel and sophisticated direct memory access (DMA) controller that can operate in either "fly-by" mode, "dual-cycle" mode, or "flow-through" mode. The DMA controller of the present embodiment supports a parametrizable number of channels, each of the channels providing support for one of the prior-noted modes of operation. The DMA controller of the present embodiment serves as bus master on the host bus and has the ability to interface with all the devices on the system. The DMA controller of the present embodiment is also optimized for zero wait state sequential transfers on the host bus. Further, the DMA controller of the present embodiment also houses an internal arbiter with programmable priority to choose arbitrate between the different channels, should more than one master that interface to the DMA controller request access to the host bus. An advantage of the present invention is that, because bus master devices are be off-loaded from the host bus, system performance can be dramatically improved. Another advantage is that the present invention provides an easy means for adding more devices to the system.</p> |
