| 摘要 |
PROBLEM TO BE SOLVED: To provide a test pattern generation method for failure verification and its device to simply prepare a test pattern with respect to a logic circuit by using an ATPG without introducing a scan circuit even if a sequence circuit is included in the logic circuit, and to provide a failure verification method and its device, and a program. SOLUTION: The sequence circuit possessed by the logic circuit is replaced by a prescribed combination circuit (step S1). Subsequently, a prescribed test pattern generation means for failure verification such as an ATPG is applied to the logic circuit after the sequence circuit is replaced by the combination circuit, thereby generating an input test pattern (step S2). The input test pattern is inputted into the logic circuit prior to the replacement of the sequence circuit by the combination circuit, thereby generating an expectation value test pattern (step S3). A test pattern for failure verification, comprising the input test pattern and the expectation value test pattern, thus generated, is used to verify the logic circuit. COPYRIGHT: (C)2005,JPO&NCIPI
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